1. Field of the Invention
The present invention relates most generally to Integrated Circuits (ICs) formed on semiconductor substrates. More particularly, the present invention relates to methods and apparatus for improving the yield of ICs from the fabrication process.
2. Description of the Related Art
ICs are often implemented by connecting together different types of functional blocks to achieve the desired IC specification. As shown in FIG. 1, some of the functional blocks most often used in IC 10 are logic 12, memory 15, including RAM 13 and register files 14, Input/Output (I/O) 18, analog/mixed signal 22 and custom blocks 28. Some examples of analog/mixed signal functions are Phase Locked Loops (timing generation, de-skewing) 24 and Digital-Analog Converters (not illustrated). Of these, I/O 18, memory 15 and analog blocks 22 are typically used as a single pre-formed unit, or hard macro, by the IC designer, whereas some of the other blocks, primarily the logic, are constructed from a set of lower level sub-blocks, or standard cells, to enable a higher degree of customization and optimization.
An IC designer typically has numerous options to implement each of the functional blocks to create the best possible design for the IC. With respect to the I/O, memory and/or analog functions, hard macros that implement the required function but which are optimized for higher speed or lower power or smaller area are available, and the IC designer chooses the hard macro best suited to the particular design.
Implementing logic functions is much more complex due to the typically large number of standard cells, ranging from tens of thousands to tens of millions, needed to implement the logic functions. Each standard cell is comprised of a predetermined number of transistors coupled together to perform a particular logic function. For example, there are standard cells that perform the functions of NAND, AND, NOR and OR gates, as well as more complicated logic functions such as single bit adders. The IC designer typically has access to different implementations of these low level functions, the different implementations targeted respectively for lower power, higher speed or smaller area. Design automation tools are necessary to analyze various implementations and obtain an optimum result when designing complex logic functions.
FIG. 2 illustrates a typical design flow for logic functions within an IC. In this particular environment, a Behavioral level description or RTL file 51 presents a logic function requirement to a synthesis tool 53. Synthesis tool 53 is coupled to a library of standard cells 55. A typical known standard cell library 55 consists of a plurality of different cell types, including the illustrated AND, NOR, flip-flop and inverter cells. Each cell will be available in several different sizes, the size referring to the size of the output driver transistors. These transistors vary in size depending on what the output of the cell is coupled to. For example, if an AND gate's output is coupled to the input of a single inverter, a small or “1×” output driver transistor will be adequate. If the cell is expected to drive the input of many other cells, larger 2× or 3× output driver transistors may be needed. Although other aspects of the cells must be adjusted depending on the size of the output driver transistors, those adjustments are considered ancillary and cells are typically only offered to designers sorted by the output driver transistor size. Although the selection of the correctly sized cell is driven by the design, it is unavoidable that a larger cell (larger output driver transistors) will have a greater delay than a smaller cell.
Synthesis tool 53 analyzes the logic function and presents the IC designer with an implementation of that function using various types of standard cells that meet the specification. Different cell sizes will be used depending on the number of other cells their output is coupled to. The implementation typically contains a list of cells required and the necessary connections between them. The file that contains the list of connections is typically called a netlist 57.
Netlist 57 and the list of cells are provided as inputs to another automation tool 59 that places the actual cells within the IC layout. Placement tool 59 uses the cell footprint and pin location information from the library 55 to place the cells so as to minimize the interconnects required by netlist 57. The placement of the cells is communicated to another tool, router 63, through a placement file (DEF) 61. Router 63 then draws the wiring between the placed cells to implement the connectivity specified in netlist 57. The wiring generated by the router and the cell level detailed layout are combined to form the IC layout database, which is stored in a GDS2 format as file 65.
One optimization target for IC design is cost. A smaller area logic circuit will allow a larger number of usable ICs per silicon wafer, reducing the cost of each IC. The IC designer's goal is to design the IC so that the specifications are met using the smallest possible silicon area. The IC designer is typically provided with multiple variants of each hard macro, the variants showing different trade offs among the variables of area, speed and power. This extends to standard cells where each logic function, for example an AND gate, has multiple different implementations, the different implementations required for different output drive strength. Standard cells with increased drive strength are typically larger than those with relatively less output drive strength. This is shown pictorially in FIG. 2 by AND cell 55a, b and c, inverter 67a, b and c, flip-flop 69a, b and c and NOR 71a, b and c. 
Although the described process and apparatus to create the smallest implementation of an IC incorporating the various building blocks that include logic functions and logic circuits functions reasonably well, it does not consider manufacturability as a key variable.
Until recently, die area was the primary factor affecting IC yield (usable dies per wafer) and hence IC cost. As the size of the various features on an IC have continued to shrink, other factors have become more important. One factor is the increased complexity of each step in process manufacturing. For example, depending on the manufacturing processes used to fabricate the IC, different problems affecting yield can manifest themselves. Certain IC fabrication plants have yield limiting problems with particular process technologies. For example, one process technology may have difficulties with contact formation between metal and polysilicon and another process technology might have difficulties with formation of transistors. Similarly, another technology or plant may have problems with metallization or diffusion formation. In some processes, increases in the leakage currents through transistors beyond the tolerance limits of the design can be a possible yield limiter.
Another factor is the large number of very small geometry features that must be realized on silicon to build an IC, each of which must be manufactured reliably to produce a usable IC. For example, to form any functional IC, many thousands to millions of vias and contacts must be formed between the layers of different materials. It has become increasingly difficult to accurately align and form each of these contacts and vias, which in turn decreases the yield of usable ICs from any given fabrication process. Similar concerns arise for metal wires, transistors and other numerous, critical features. As these problems are statistical in nature, their significance varies depending on the particular IC design. Different problems may be more or less acute for a given IC when different fabrication processes at different plants are used. The current method to use area as the sole indicator of yield is increasingly less determinative. A method and apparatus for implementing IC designs that improves the true yield of the IC considering the process factors described above would be desirable.